1. Field of the Invention
The present invention generally relates to a semiconductor manufacturing process, and more particularly to a method for forming a gate electrode by a damascene process.
2. Description of the Prior Art
In the integrated circuit (IC) industry, semiconductor devices are being manufactured to contain metal oxide semiconductor (MOS) transistors which having conductive gate electrodes usually formed from a damascene process or a non-damascene process.
In conventional non-damascene process, it is performing lithography process to form the gate electrode. However, the length of the gate electrode is limited by lithography capability. The gate etch process window is narrow because of the requirement of gate sidewall profile, gate residue free, and high etch selectivity to gate dielectric.
The conventional damascene process requires dummy gate removal steps. First, a gate electrode opening is formed first in a dielectric layer. After the opening is formed, the opening filled with a deposited conductive material where chemical mechanism polishing of the conductive material is used to confine the conductive material to the opening, and only the opening. Then, the dielectric layer is removed to form a gate structure. However, the length of the gate electrode is still limited by lithography capability. The silicon substrate is damaged and contaminated in dummy gate removal steps. Thus, it is a major concern to the quality of the dielectric. Another disadvantage is that the source/drain region is formed before gate dielectric growth, wherein the gate dielectric growth is in a high temperature, so the high temperature step enhances the short channel effect.
An object of the invention is to use a damascene process to control the gate length easily in a device.
It is another object of the invention that a thin gate layer is provided on the gate dielectric layer before performing the damascene process such that the substrate can be protected and residue can be reduced in dummy gate removal steps.
A further object of the invention is to prevent from short channel effect by forming the source/drain region after the gate dielectric growth.
In accordance with the present invention, a method for forming a transistor in integrated circuits, wherein the gate electrode of the transistor is formed by a damascene process, is provided. First, a substrate is provided with a gate dielectric layer thereon and a first gate layer is formed on the gate dielectric layer. Next, a first silicon oxide layer is deposited on the first gate layer and an opening through the first silicon oxide layer is formed by an etching process. Then, a first spacer is formed on sidewalls of the first silicon oxide layer in the opening and then the opening is filled with a second gate layer. Following, the first silicon oxide layer and the first spacer are removed to form a gate structure. The first gate layer and the gate dielectric layer around the gate structure are removed. Then, a lightly doped drain, a second spacer, and a source/drain region are formed sequentially in the transistor.